First, a typical configuration of a conventional active matrix type liquid crystal display device will be described briefly with reference to FIG. 5, which is an equivalent circuit diagram schematically showing a portion thereof corresponding to one pixel. An active matrix type liquid crystal display device has a liquid crystal panel (not illustrated), which has liquid crystal pixels arrayed in a matrix (for example, composed of A columns and B rows (where A and B are natural numbers)), with each liquid crystal pixel located at the intersection between a gate line PXn (where n is a natural number equal to or smaller than A) and a signal line (source line) Ym (where m is a natural number equal to or smaller than B) on the liquid crystal panel. This liquid crystal pixel is represented equivalently by a liquid crystal capacitance CLC. Usually, in parallel with the liquid crystal capacitance CLC is connected an auxiliary capacitance CS. One end of the liquid crystal capacitance CLC is connected to a pixel transistor Tr for driving the pixel, and the other end of the liquid crystal capacitance CLC is connected to a common electrode so as to receive a predetermined reference voltage Vcom.
The pixel transistor Tr is built as an N-channel TFT (thin-film transistor) of an insulated-gate field-effect type, with the drain electrode D thereof connected to the signal line Ym to receive an image signal Vsig, and with the source electrode S thereof connected to one end of the liquid crystal capacitance CLC, i.e., to the pixel electrode. The gate electrode G of the pixel transistor Tr is connected to the gate line PXn so as to receive a gate pulse having a predetermined gate voltage Vgate. Between the liquid crystal capacitance CLC and the gate electrode G is formed a coupling capacitance CGS. This coupling capacitance CGS is the sum of the floating capacitance between the pixel electrode and the gate line PXn and the parasitic capacitance between the source region and gate region inside the pixel transistor Tr, the latter, namely the parasitic capacitance, being dominant and considerably varying from one pixel transistor Tr to another.
Now, the voltage waveforms observed at relevant points within the single pixel shown in FIG. 5 will be described with reference to FIG. 6. In FIG. 6, the lapse of time is taken along the horizontal axis, and, with respect to the pixel transistor Tr corresponding to that single pixel, the voltage waveform at the gate electrode G thereof (represented by the solid line 200 in FIG. 6) and the voltage waveform at the source electrode S thereof (represented by the solid line 201 in FIG. 6) are plotted relative to the reference voltage Vcom.
First, during the selection period of the pixel, when a gate pulse with a voltage Vgate is applied to the gate electrode G, the pixel transistor Tr turns on. At this point, the image signal Vsig fed from the signal line Ym is written via the pixel transistor Tr to the liquid crystal pixel, with the result that the potential at the source electrode S becomes equal to Vsig, achieving so-called sampling. Next, during the nonselection period of the pixel, the gate pulse ceases to be applied, and instead a low-level gate voltage is applied, causing the pixel transistor Tr to turn off. The written image signal, however, is held by the liquid crystal capacitance CLC.
Here, the low-level gate voltage is a voltage that is lower than the voltage Vgate so that, when applied to the gate electrode G of the pixel transistor Tr, it causes it to turn off. With respect to a given pixel, the period of time from the start of the selection period of that pixel through the nonselection period thereof until the selection period thereof starts again is referred to as one field.
At the transition from the selection period to the nonselection period, the gate pulse, which is a square wave, abruptly falls from a high level to a low level. This causes the electric charge stored in the liquid crystal capacitance CLC to be instantaneously discharged through the coupling capacitance CGS described above. This produces a voltage shift ΔV1 in the image signal Vsig written to the liquid crystal pixel. That is, the voltage at the source electrode S lowers by ΔV1. Since the coupling capacitance CGS varies from one pixel to another in the liquid crystal display device, the voltage shift ΔV1 also varies accordingly. Thus, the ΔV1 drop in the voltage eventually produces a periodic variation in the screen displayed on the liquid crystal panel, resulting in so-called flickers and afterimages, which remarkably degrade the display quality.
Incidentally, in a liquid crystal pixel, an image signal is written thereto during the selection period thereof, and, during the subsequent nonselection period thereof, the written image signal is held. This makes up a field. The transmissivity of a liquid crystal pixel during one field is determined by the effective voltage that is applied to the liquid crystal during that period. Accordingly, the pixel transistor Tr there needs to be designed to permit the passing therethrough of an on-state current that is needed to complete the write operation within the selection period. Moreover, to obtain a sufficiently high effective voltage to keep the liquid crystal pixel lit during the period of one field, the pixel transistor Tr needs to be designed to permit as little leak current as possible during the nonselection period (or holding period). The variation of the effective voltage is more influenced by the nonselection period, which lasts far longer than the selection period. Thus, the aforementioned voltage shift ΔV1, which occurs when, after the charging of the liquid crystal capacitance CLC, the pixel transistor Tr turns off, greatly influences the effective voltage that is applied to the liquid crystal, degrading the display quality of the liquid crystal panel.
A conventional approach to reducing the absolute value and variation of the voltage shift ΔV1 is to give a comparatively high capacitance to the auxiliary capacitance CS, which is connected in parallel with the liquid crystal capacitance CLC. The purpose is to permit the auxiliary capacitance CS to store in advance sufficient electric charge to compensate for the electric charge that is discharged through the coupling capacitance CGS. This approach has a disadvantage: the auxiliary capacitance CS is formed in the liquid crystal pixel region, and therefore increasing its size results in sacrificing the pixel aperture ratio, leading to insufficient display contrast.
An example of a solution to this problem of the voltage shift in a conventional active matrix type liquid crystal display device is disclosed in Japanese Patent Application Laid-Open No. H6-3647 (hereinafter referred to as “Patent Publication 1”). FIG. 7 shows, with respect to the pixel transistor Tr, the voltage waveform at the gate electrode G thereof (represented by the solid line 300 in FIG. 7) and the voltage waveform at the source electrode S thereof (represented by the solid line 301 in FIG. 7) plotted relative to the reference voltage Vcom, as observed when the technique disclosed in Patent Publication 1 is adopted.
According to the technique disclosed in Patent Publication 1, as shown in FIG. 7, immediately before the transition from the selection period to the nonselection period, the voltage level applied to the gate electrode G is first lowered to a second high-level gate voltage Vgate2 that is lower than a first high-level gate voltage Vgate1, and is then made to fall further to a low-level gate voltage to produce a gate pulse PGP. In this way, the voltage shift (ΔV2 in FIG. 7) in the image signal Vsig written can be reduced.
The timing with which the voltage level of the gate pulse PGP is lowered from the first high-level gate voltage Vgate1 to the second high-level gate voltage Vgate2 is on completion of the write operation so as not to influence the write operation to the liquid crystal pixel during the selection period. Specifically, the voltage fed as the gate pulse PGP to the gate electrode G is first lowered from the first high-level gate voltage Vgate1 to the second high-level gate voltage Vgate2, and is then, after transition to the nonselection period, made to fall further to the low-level gate voltage. This reduces the potential difference between the gate line PXn and the source electrode S at the time point of transition from the selection period to the nonselection period, and thus permits effective reduction of the voltage shift (ΔV2 in FIG. 7) (that is, the voltage shift ΔV2 can be made smaller than the voltage shift ΔV1).
Now, a practical example of the drive circuit adopted in Patent Publication 1 mentioned above for driving an active matrix type liquid crystal display device will be described with reference to FIG. 8. In FIG. 8, the active matrix type liquid crystal display device has a display section including liquid crystal pixels LP arrayed in a matrix and pixel transistors Tr that drive those liquid crystal pixels LP respectively. In FIG. 8, such components as are found also in FIG. 5 are identified with the same reference symbols, and their explanations will not be repeated. In FIG. 8, only the liquid crystal pixels that correspond to one row are shown.
The gate electrodes G of the pixel transistors Tr are connected, through gate lines PX1, PX2, PX3, PX4, . . . respectively, to a vertical scanning circuit 101. Through these lines, gate pulses PGP1, PGP2, PGP3, PGP4, . . . are applied, sequentially through one line after another, to the respective pixel transistors Tr so that one of them is selected at a time. The drain electrodes D of the pixel transistors Tr are connected through a signal line Ym to a horizontal drive circuit 102 so that an image signal Vsig is written, through the currently selected pixel transistor Tr, to the corresponding liquid crystal pixel LP.
The vertical scanning circuit 101 is built as a shift register 103. This shift register 103 has D flip-flops 104 connected in multiple stages, each D flip-flop 104 being composed of a pair of inverters 105 and 106 of which the output terminals are connected together. Each inverter is connected through a P-channel drive transistor 107 to the mid point between a pair of serially connected voltage-division resistors R101 and R102, and is connected through an N-channel drive transistor 108 to ground. This pair of drive transistors 107 and 108 drives the inverters 105 and 106 by being made to conduct in response to shift clock pulses VCK1 and VCK2 and the inverted versions of these pulses.
The output terminals, connected together, of the pair of inverters 105 and 106 are connected to the input terminal of a third inverter 109, and the output pulse of the D flip-flop of each stage appears at the output terminal of the third inverter 109. The output pulse is used as the input to the D flip-flop of the next stage. When a start signal VST is fed to the D flip-flop of the first stage, the shift register 103 outputs, sequentially from one stage thereof after another, output pulses that are half a period out of phase with one another. The output pulse from each stage and the output pulse from the preceding stage are subjected to the logic operation performed by a NAND gate element 110, and is then inverted by an inverter 111. In this way, the gate pulses PGP1, PGP2, PGP3, PGP4 are obtained.
The serially connected voltage-division resistors R101 and R102 are, at one end, connected to a source voltage VVDD, and, at the other end, connected through a switching transistor 114 to ground. A control voltage VCKX is periodically applied to the gate electrode of the switching transistor 114. When the switching transistor 114 is off, the source voltage VVDD is fed as it is to the shift register 103, so that the voltages of the gate pulses PGPn (where n is a natural number) are all equal to the source voltage. By contrast, when the switching transistor 114 turns on, a voltage obtained through voltage division by the factor of the resistance ratio of the resistors R101 and R102 is fed to the shift register 103, so that the voltages of the gate pulses PGPn become accordingly lower.
In this example, the control voltage VCKX that is applied to the gate electrode of the switching transistor 114 shows pulse-like level shifts according to the horizontal synchronizing signal. In this example, the horizontal period is set at 63.5 μs, and this period corresponds to the selection period of one gate line. At the very end of each horizontal period, the control voltage VCKX turns to a high level and remains thereat for a period of 6 to 8 μs. This period is so set as not to influence the write operation of the image signal during the selection period. Specifically, it is on completion of the writing of the image signal to all the pixels on the selected gate line, which proceeds sequentially to one pixel after the another, that the control voltage VCKX turns to a high level. When the control voltage VCKX turns to a high level, the switching transistor 114 turns on, with the result that the level of the supply voltage fed to the shift register 103 lowers, for example, from the level of the source voltage VVDD, which is set equal to the first high-level gate voltage, namely 13.5 V, to that of the second high-level gate voltage, which is set at about 8.5 V. The amount of voltage lowering here can be appropriately set by appropriately setting the resistance ratio of the pair of voltage-division resistors R101 and R102.
In response to this change in the supply voltage, for example, the n-th (where n is a natural number) gate pulse PGPn changes its level stepwise from 13.5 V to 8.5 V within one horizontal period. In the next horizontal period, a gate pulse PGPn+1 corresponding to the (n+1)th gate line is generated, and this gate pulse likewise changes its level stepwise. Through operations like these, the vertical scanning circuit, immediately before making the voltage level applied as each gate pulse PGPn fall, first lowers the voltage level of the gate pulse PGPn and then makes it fall further. In this way, the voltage shift in the image signal Vsig written to the pixel can be reduced.
As described above, with the technique disclosed in Patent Publication 1 mentioned above, by making the gate pulse PGPn fall stepwise, it is possible to effectively reduce the voltage shift ΔV2 in the image signal Vsig.
However, in the above described practical example disclosed in Patent Publication 1, the gate pulse PGPn that falls stepwise is produced by varying between the source voltage VVDD and the voltage VVDD×R102/(R101+R102) the supply voltage fed to the shift register 103 functioning as a gate driver. As a result, the circuit including the shift register 103 as a whole has a complicated, large-scale circuit configuration, and requires large amount of current to operate. Thus, the driver occupies a large area.
Moreover, a voltage obtained by dividing the source voltage VVDD with the resistors R101 and R102 is used as the supply voltage to the shift register 103, and this divided voltage shows high current dependence. This tends to make unstable the supply voltage to the shift register 103 and the voltage of the gate pulse PGPn.
Moreover, every time the supply voltage to logic elements such as the shift register 103 is switched by turning the switching transistor 114 on and off, a surge voltage appears in the voltage of the gate pulse PGPn, degrading the display quality. In addition, whereas logic elements such as the shift register 103 usually operate from a supply voltage of 5 V or less, in this example they are made to operate from a far higher voltage, for example 13.5 V to 8.5 V, resulting in extremely high power consumption.